Website Synopsys Inc
At Synopsys, we are at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. In addition to the traditional EDA tools and IP we also provide design services to enable our customers with end-to-end SoC design solution in advanced technology nodes. If you share our passion for innovation, we want to meet you. Our System Solutions team delivers tool flow, methodology deployment, design creation and implementation expertise to enable leading edge customers to complete their challenging SoC designs. Our services include customer specific design assistance, design flow, RTL-to-GDSII implementation for blocks, sub-systems, and full SoCs, as well as executing full SoC turnkey designs from specification-to-parts. Our customers range from industry leaders to start-ups and government agencies, developing products for applications such as telecommunications, wireless, industrial, automotive, AI, and high-performance computing. As a Senior I Verification Engineer you will be responsible for contributions towards technical solutions, developing strategies, and creating environments that assure the correctness and completeness of highly complex ASIC and FPGA devices. Armed with verification experience and applying industry leading methods with state-of-the-art tools, you will participate in the challenge of conceptualizing, planning, developing, and executing test environments that wring out even the most difficult design bugs. Exposure to a wide variety of technologies and solutions provides an endless stream of complex new and exciting verification experiences.
- Bachelor’s Degree in Electrical, Computer Engineering, or Computer Science.
- 6+ years of work experience in design or verification using hardware description languages.
- Knowledge of System Verilog HDL and scripting languages such as Perl, Python, Ruby.
- Good Object-Oriented programming background.
- Understand standard protocols such as PCIe, DDR4, GDDR, HBM, AMBA are preferred.
- Demonstrated experience in UVM methodology-based verification.
- Participate as a key contributor.
- Execute against verification test plans.
- Understand and apply modern verification processes and flows in different environments, methods, standards, and experienced with tools such as Synopsys VCS and Verdi.
- Excellent written and verbal communication skills.
Preferred Additional Experience
- System Verilog/C++ co-simulation.
- Overall knowledge of the SoC development process.
- RTL design.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
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