ASIC Digital RTL Design Engineer – 37004BR – Synopsys Inc

Website Synopsys Inc

Introduction

  • At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security.
  • Our Digital Team is seeking for great Senior Engineer to join our talented team.
  • If you are an experienced Digital Senior Engineer who wants to join a team of experts in dynamic digital design with latest process technologies and a great team player, this can be a perfect position for you.

Opportunities

  • SNPS is the world number one IP provider. To be trained and developed by many experts from around the world and talented highly motivated Viet Nam engineering team
  • Professional, innovative, fair and fun working environment. Strong culture company.
  • Competitive salary and benefit. Strong support from company for health: Insurance, Sport clubs: Football, Ping-Pong, Badminton, Yoga, Zumba …
  • Strong support from company for team building, social activities: Team trip, Family Day…
  • Opportunity to get in touch with the complete design flow of a real complicated Analog Mixed Signal Design from specification to silicon.
  • Chance to work with bleeding edge technologies that enable Data Center, AI/ML, 5G applications.
  • Clear career path of self-development to either Technical Expert or Design Leader/Manager
  • Travel to USA, Europe and Asia for training or on-site support.

Job Descriptions

  • Responsible for specification development, architecture design and RTL development for High Bandwidth Interface PHY IP and Test chip.
  • Define synthesis design constraints, resolve issues related to STA and Gate level simulation.
  • Collaborate with Verification team and review the Verification plan mapping with specification.
  • Collaborate with Controller and maybe Zebu team for sub system design and verifications.
  • Familiar with RTL to GDS flow to follow up with other teams during the logic implementation phases.
  • Collaborate with Lab team to debug silicon issues related to logic design.
  • Perform Project leadership role if required.
  • May work directly with customer to resolve technical issues related to RTL.
  • Contribute to the digital flow development.
  • Train junior RTL engineers.

Skills Requirements

  • BS/MS/PhD in Electronics Engineering, Telecommunications.
  • 5+ years of experience in RTL design for ASIC or PHY IP.
  • Familiar with tool VCS, Verdi, Spyglass or similar tools
  • Solid knowledge on clock domain crossing
  • Strong scripting skills (Perl, tcl, Python)
  • Familiar with APB, JTAG
  • Strong communication both verbally and in writing
  • Experience in Analog Mixed Signal IP is a big plus
  • Good English in both speaking and writing.
  • Highly responsible, result oriented.
  • Self-motivated and highly enthusiasm in technology and solving problems

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

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