ASIC Digital Design Engr, Sr II – 41330BR -Synopsys Inc

Website Synopsys Inc

Opportunities

  • SNPS is the world number one IP provider. To be trained and developed by many experts from around the world and talented highly motivated Viet Nam engineering team
  • Professional, innovative, fair and fun working environment. Excellent culture company.
  • Attractive salary and benefit. Great support from company for health: Insurance, Sport clubs: Football, Table tennis, Badminton, Yoga, Zumba …
  • Dedicated support from company for team building, social activities: Team trip, Family Day…
  • Opportunity to get in touch with the complete design flow of a real complicated Analog Mixed Signal Design from specification to silicon.
  • Chance to work with bleeding edge technologies that enable Data Center, AI/ML, 5G applications.
  • Clear career path of self-development to either Technical Pro or Design Leader/Manager
  • Travel to USA, Europe and Asia for training or on-site support

Candidates apply for this position can be either RTL Designer or Design Verification Engineer.RTL Designer Job Descriptions

  • Responsible for specification development, architecture design and RTL development
  • Define synthesis design constraints, resolving STA issue as well as Gate level simulation issue
  • Working with Verification team and review the Verification plan mapping with specification
  • Steady knowledge from RTL to GDS as well as silicon bring up experiences
  • Perform Project leadership role if required.
  • Communication directly with customer as well as cross-team collaboration.
  • Drive the digital flow development
  • Represents the organization on business unit

RTL Designer Skills Requirements

  • BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications.
  • 6+ years of experience in RTL-to-GDS design
  • Deep technical knowledge of RTL-to-GDS full design flow
  • Solid scripting skills (Perl, tcl, Python)
  • Solid communication both verbally and in writing
  • Experience in Analog Mixed Signal is a big plus

Design Verification Enginer Job Descriptions

  • Work in a Digital and Verification Development team during the development and validation of complex digital mix signals for high-speed interface IP.
  • Test planning, checklist, Coverage and Assertion planning
  • Hands on experience in creating detailed Verification Environment from Functional Specifications
  • Applying advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification.
  • Writing test cases, checkers, and coverage that implement the verification test plan.
  • Debug of simulations, including those of real signals modeled using SV for analog
  • RTL, GLS & Co-simulations & coverage closure
  • Participate in technical reviews and contribute effectively
  • Participate in customer support with bring-up of IP in customer simulation environment
  • Follow and improve development process ensuring high quality output.

Design Verification Engineer Skills Requirements

  • BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications.
  • 6+ years of experience in Design Logic Verification
  • Solid skill with VCS/Verdi simulation tools, Formal verification tool (vc_formal)
  • Solid knowledge of UVM(Universal Verification Methodology), SVA (System-Verilog Assertion) and UPF (Unified Power Format)
  • Solid debug skills and demonstrated experiences in Perl /TCL/Python scripting is a plus
  • Highly responsible, result oriented

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