ASIC Digital Design Engr, II – 41907BR – Synopsys Inc

Website Synopsys Inc

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

Senior ASIC Digital Design Engineer

As an ASIC Design, Implementation and Verification Engineer you should have experience in both back-end and front-end ASIC development flows to provide targeted support to mixed-signal PHY semiconductor IP customers. The successful candidate will exercise skills in a variety of tasks including but not limited to RTL coding, test bench and test case development, linting, synthesis, STA, place & route, DRC/LVS, silicon debug, and documentation. The position requires extensive interaction with customers including periodic international travel to assist them at their sites.

Key Qualifications

  • Must have BSEE in EE with 2+ years of relevant experience or MSEE
  • Experience in ASIC RTL design and verification
  • Strong Verilog, system Verilog, PERL, and TCL skills
  • Knowledge in DFT
  • Knowledge in silicon debugging
  • Demonstrates good communication skills in English
  • Demonstrates good analysis and problem-solving skills
  • Knowledge of high speed interface protocols is a plus

Preferred Experience

  • Participates in the generation of data books, application notes, and white papers
  • Generates test benches and test cases
  • Performs RTL and gate-level SDF-annotated simulations
  • Experience of DFT is a big plus
  • Assists test engineers with silicon evaluation
  • Develops and executes functional test/verification plans
  • Writes synthesizable RTL code for circuit portions of integrated circuits

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

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